1. Field of the Invention
The present invention relates generally to semiconductor memories and more specifically to a low voltage and low power static random access memory (SRAM)
2. Description of the Background Art
Digital devices are constantly becoming more pervasive in numerous applications, such as personal computers, telecommunications, consumer electronics, and the like. Consequently, the use of digital memory also constantly increases. By far, the most widely used type of semiconductor memory is the dynamic-random-access memory (DRAM). DRAMs, due to their high packing density and resulting small device footprint for a given number of memory locations, provide a low cost memory alternative. However, DRAMs require a great deal of overhead circuitry, including circuits to periodically refresh the state of each of the DRAM bit cells and thereby retain stored data.
Another widely used memory alternative is the static random access memory (SRAM). SRAMs do not require refresh circuitry, are more easily integrated into other devices and systems, and generally have a faster access time than many other memory device alternatives. However, SRAMs have a lower packing density, a larger resulting device footprint for a given number of memory locations and thus, a higher cost per memory size than, for example, DRAMs. SRAMs therefore tend to be more widely used where, for example, avoidance of system complexity (due to refresh circuitry and/or other characteristics of memory device alternatives) justifies their higher cost.
While thus desirable due to easy integration and other factors, SRAM use is limited based upon source voltage and power consumption requirements. One reason is portability. Reduced electrical requirements would allow portable systems containing SRAM, such as pagers, hand-held global positioning systems (GPS) and pacemakers (to name just a few examples), to utilize a lower voltage power supply and/or utilize a given power supply (e.g., a battery) for a longer period.
Reduced electrical requirements would further allow a given power supply to support an increased amount of SRAM. This would result in an application-oriented system utilizing some general purpose components (e.g., microcontrollers or microprocessors) which can store more instructions, can have greater functionality, and/or can store more data. A pager, for example, might thus be able to support transmission of volumes of text and/or other media A GPS might store a planned trip, directions traveled, etc. A pacemaker might record and/or accommodate specific scenarios, perform self testing, call a doctor, etc. Numerous other general and special-purpose systems would also benefit for these and other reasons.
Until recently, conventional SRAMs have provided a typical operating range of 2.7 v&lt;VCC&lt;3.6 v. More recently, however, methods such as element-size reduction, process reduction and final test sorting have been utilized with increasing frequency and with some success. Element-size reduction includes, for example, decreasing the size of the transistor channel, thereby reducing the electrical requirements for transistor operation. Similarly, process reduction involves decreasing the geometry of some, most or even all electrical elements by further optimizing processing techniques. Final test sorting involves testing devices produced at tighter tolerances than standard devices for specific characteristics. Due to process variations, certain devices will tend to have certain characteristics that are enhanced while other characteristics (hopefully, less important ones) might be less ideal. Thus, devices with lower voltage and/or power requirements might be found by testing for these specific characteristics.
Through these increasingly utilized conventional techniques, devices having voltages as low as 1.8 v (and some with desirable power reductions) have been made available in some quantity. Unfortunately, these techniques have limitations. Geometry reduction techniques can be extremely expensive and are subject to physical limitations with respect to tooling and process capabilities, device functionality, interoperability, and/or containment, as well as other factors. Final test sorting typically produces only a limited yield, at additional expense and often with a compromise in other desirable device characteristics. As with geometry reduction, final test sorting will provide limited improvement beyond which these and/or other undesirable consequences will result.
Thus, a new approach is required to further lower the VCC operating range of SRAM systems.
Therefore, what is needed and what has been invented is a low voltage and low power memory system which operates at lower voltage levels than currently known technology, and which would overcome the foregoing deficiencies.